Writeback-aware partitioning and replacement for last-level caches in phase change main memory systems
نویسندگان
چکیده
منابع مشابه
DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems
Read and write requests from a processor contend for the main memory data bus. System performance depends heavily on when read requests are serviced since they are required for an application’s forward progress whereas writes do not need to be performed immediately. However, writes eventually have to be written to memory because the storage required to buffer them on-chip is limited. In modern ...
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Variability in generational behavior of cache blocks is a key challenge for cache management policies that aim to identify dead blocks as early and as accurately as possible to maximize cache efficiency. Existing management policies are limited by the metrics they use to identify dead blocks, leading to low coverage and/or low accuracy in the face of variability. In response, we introduce a new...
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The cost of last-level cache misses and evictions depend significantly on three major performance-related characteristics of DRAM-based main memory systems: bank-level parallelism, row buffer locality, and write-caused interference. Bank-level parallelism and row buffer locality introduce different latency costs for the processor to service misses: parallel or serial, fast or slow. Write-caused...
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The design of an effective last level cache(LLC) continues to be an important issue in processor‘s performance. Recent works on high performance caches have shown that cache bypassing is an effective technique to enhance the performance of last level caches. However, commonly used inclusive cache hierarchy cannot benefit from this technique because bypassing inherently breaks the inclusion prop...
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ژورنال
عنوان ژورنال: ACM Transactions on Architecture and Code Optimization
سال: 2012
ISSN: 1544-3566,1544-3973
DOI: 10.1145/2086696.2086732